1. Field of the Invention
The present invention relates to a semiconductor device structure and method of manufacturing the same, and in particular relates to a structure of a silicon LSI (Large Scale Integrated) circuit and a method for manufacturing the same.
2. Background Art
Conventionally, performance and function of the silicon LSI circuit have been improved by contracting the design rule step by step based on scaling in computer graphics. In order to improve yields in the manufacturing process of the silicon LSI circuits, it is indispensable to improve the technique of forming wiring and contacts for connecting elements.
In manufacturing a silicon LSI circuit, a plurality of elements such as MOSFETs (Metal Oxide Semiconductor Field Effect Transistors), which are selectively arranged on the silicon substrate, are connected using contact plugs for wiring for forming a desired electronic circuit.
Furthermore, in order to provide a complicated circuit, wiring is formed by a multiple layered structure through interlayer insulating layers, and in each layer, wiring is formed by connections using contact holes, which are filled with a conductive material. If the contact hole cannot be formed at a prescribed connecting position, then the circuit becomes an open circuit to cause malfunction. If the contact area is small in the case of connection using contact holes, the contact resistance increases which results in deterioration in the circuit performance. Accordingly, it is desired to integrate circuits with the lowest possible contact resistance.
Regarding the multiple layered wiring, a structurally simple example is described with reference to FIGS. 5A-5C. FIG. 5A shows a method for directly connecting a first contact plug 24 and a second contact plug 26.
As shown in FIG. 5A, on a semiconductor substrate 21, an element separating insulating film 22, a first interlayer insulating film 23, the first contact plug 24, a second interlayer insulating film 25, and the second contact plug 26 are arranged.
The first contact plug 24 and the second contact plug 26 are directly connected to each other by making the upper end of the first contact plug 24 in contact with the lower end of the second contact plug 26. The upper end surface of the first contact plug 24 is displaced by a distance A1 with the lower end surface of the second plug 26. This displacement is caused by mechanical error.
FIG. 5B shows one of methods for connecting the first contact plug 34 and the second contact plug 37 by inserting an electrically conductive pad 35 (for example, made of a metal silicide) between the upper end surface of the first contact plug 34 and the lower end surface of the second contact plug 37.
As shown in FIG. 5B, on a semiconductor substrate 31, an element separating insulating film 32, a first interlayer insulating film 33, the first contact plug 34, a second interlayer insulating film 36, and the second contact plug 37 are arranged. As seen in the figure, there is a displacement with a distance A2 between the first contact plug 34 and the second contact plug 37. In addition, there is a displacement with a distance of A3 between the pad 35 and the second contact plug 37. These displacements of A2 and A3 are caused by mechanical errors, similar to the case of A1 shown in FIG. 5A.
The projection area of the pad 35, inserted between the upper end surface of the first contact plug 34 and the lower end surface of the second contact plug 37, is larger than the planer area of the contact hole in the lower layer. This pad 35 is formed after forming the first contact plug 34 by forming a film of a material used for the pad and by machining the film by photolithography. Accordingly, the alignment margin, corresponding to an allowable dimensional tolerance, expands by a half of the difference between the pad size and the surface area of the contact plug.
FIG. 5C shows a method, in which, without forming a contact hole, one contact plug 45 is formed by making the second contact hole penetrate from the second insulating film to the substrate surface.
As shown in FIG. 5C, there are provided on a semiconductor substrate 41, an element separating insulating film 42, a first interlayer insulating film 43, a second interlayer insulating film 44, and a contact plug 45.
Another example of the method shown in FIG. 5C using the contact plug is a conventionally known memory cell, that is, DRAM (Dynamic Random Access Memory) having a contact plug. An example of the cross-sectional structure of this type of memory cell is explained with reference to FIG. 6. In this structure, wiring for calling signals, which is called a bit line or a signal line, is formed under the layer lower than the charge accumulation capacitor 60.
A selectively formed element separating insulating film 52 and a MOSFET film are formed on the P-type silicon substrate, and on these films, an n-type conduction-type gate electrode 53 made of polysilicon is formed through a silicon oxide gate insulating film.
A first interlayer insulating film 56 is formed so as to cover the element separating film 52 and the MOSFET. In order to connect the source-drain regions 51 and the first wiring layer formed on the first interlayer insulating film 56, polysilicon plugs 54 and 55 are formed. The bit wiring 57 on the first interlayer insulating film 56 is made of tungsten suicide. A second interlayer insulating film 58 is formed so as to cover the bit wiring. A bottom electrode 59 of the capacitor is formed on the second interlayer, a capacitor dielectric film 60 is formed so as to cover the bottom electrode 59, and the upper layer of the capacitor dielectric film 60 is an upper electrode 61. The bottom electrode 59, the capacitor dielectric film 60, and the upper electrode 61 constitute a charge accumulation capacitor.
In the conventional silicon LSI circuit shown in FIG. 5A, the mask alignment accuracy is not quite high because it depends largely on machine accuracy. If the alignment shifts more than a half of the diameter of the contact plug, the contact area is reduced and the contact resistance increases.
When the second contact plug is formed on the location of the first contact plug, a shift in the mask alignment of more than a half of the diameter of the contact plug results in the failure of the device.
In the case of the method shown in FIG. 5B, when a mask processor is used for arranging the pad, the position of the pad depends on the alignment accuracy, and the position of the pad is not accurate enough to connect the contact plugs on both sides of the pad.
In the case of the method shown in FIG. 5C, since the long contact plug is formed, excessive etching time is normally set considering the homogenity of the dry etching in the dry etching of the surface. Thereby, too much of the silicon substrate near the contact plug is removed too much such that the electrical property of the substrate is changed, which causes the problem of disturbing the formation of the contact plug in an accurate alignment. When the diameter of the contact plug is small and the depth of the contact plug is large, that is, when the aspect ratio of the contact hole is large, the problem arises that throughput becomes low and contact resistance becomes high.
When it is necessary to fill silicon as a plug material in a contact hole, which has a large aspect ratio, filling is normally carried out by CVD (Chemical Vapor Deposition). However, if the amount of the material gas supplied to the reaction chamber is not reduced sufficiently, taking the mean free path of the particles in the space into consideration, the contact hole will not be filled with silicon, and voids or seams are generated in the contact hole. If the amount of silicon gas is reduced in order to prevent generation of voids or seams, the throughput of the filling process is reduced.